Shady Agwa - TrIM, Triangular Input Movement Systolic Array for

Journal article

Cristian Sestito, Shady O. Agwa, T. Prodromakis
IEEE Transactions on Circuits and Systems Part 1: Regular Papers, 2024

Cite

APA Click to copy
Sestito, C., Agwa, S. O., & Prodromakis, T. (2024). TrIM, Triangular Input Movement Systolic Array for Convolutional Neural Networks: Architecture and Hardware Implementation. IEEE Transactions on Circuits and Systems Part 1: Regular Papers.

Chicago/Turabian Click to copy
Sestito, Cristian, Shady O. Agwa, and T. Prodromakis. “TrIM, Triangular Input Movement Systolic Array for Convolutional Neural Networks: Architecture and Hardware Implementation.” IEEE Transactions on Circuits and Systems Part 1: Regular Papers (2024).

MLA Click to copy
Sestito, Cristian, et al. “TrIM, Triangular Input Movement Systolic Array for Convolutional Neural Networks: Architecture and Hardware Implementation.” IEEE Transactions on Circuits and Systems Part 1: Regular Papers, 2024.

BibTeX Click to copy

@article{cristian2024a,
  title = {TrIM, Triangular Input Movement Systolic Array for Convolutional Neural Networks: Architecture and Hardware Implementation},
  year = {2024},
  journal = {IEEE Transactions on Circuits and Systems Part 1: Regular Papers},
  author = {Sestito, Cristian and Agwa, Shady O. and Prodromakis, T.}
}

Abstract

Modern hardware architectures for Convolutional Neural Networks (CNNs), other than targeting high performance, aim at dissipating limited energy. Reducing the data movement cost between the computing cores and the memory is a way to mitigate the energy consumption. Systolic arrays are suitable architectures to achieve this objective: they use multiple processing elements that communicate each other to maximize data utilization, based on proper dataflows like the weight stationary and row stationary. Motivated by this, we have proposed TrIM, an innovative dataflow based on a triangular movement of inputs, and capable to reduce the number of memory accesses by one order of magnitude when compared to state-of-the-art systolic arrays. In this paper, we present a TrIM-based hardware architecture for CNNs. As a showcase, the accelerator is implemented onto a Field Programmable Gate Array (FPGA) to execute the VGG-16 and AlexNet CNNs. The architecture achieves a peak throughput of 453.6 Giga Operations per Second, outperforming a state-of-the-art row stationary systolic array up to <inline-formula> <tex-math notation="LaTeX">$\sim 3 \times $ </tex-math></inline-formula> in terms of memory accesses, and being up to <inline-formula> <tex-math notation="LaTeX">$ \sim 11.9 \times $ </tex-math></inline-formula> more energy-efficient than other FPGA accelerators.