Abstract

The AI revolution shows the ever increasing performance demands of AI applications like Deep Neural Networks DNNs which consist of tens of layers and do computations on tens of millions of data weights [1]. Conventional Von Neumann architectures are currently struggling to meet these emerging performance demands with deep memory hierarchies to bridge the processor-memory performance gap [2]. Emerging technologies (like RRAMs) have meanwhile shown a real promise to address the increasing challenges of the conventional computing technology. While the main direction of research is focussing on exploiting the analogue memory attributes of RRAMs specially for analogue computing crossbars [3], this paper focuses on a different perspective of building high-density and digital-friendly RRAM-based memory that is a good alternative to the SRAM-based Last-Level Caches LLCs. This digital RRAM-based memory with conventional 1T1R bit-cells is proposed to be an on-chip gigantic data reservoir, with much higher density than SRAMs, to bridge the memory gap. The paper also shows that the digital RRAM-based memory is capable of doing robust bit-line compute which opens the door for digital in-memory computing architectures that can mitigate the Von Neumann bottleneck while adopting RRAM’s high-density promise. Unlike analogue RRAM crossbars, RRAMs’ digital in-memory computing capability should inherit the large scalability and the fast time-to-market of the digital domain with less engineering effort for optimisation as there is no need any more to build DACs and ADCs.