Shady Agwa - Design techniques for variability mitigation

Journal article

Shady O. Agwa, Eslam Yahya, Y. Ismail
2013

Cite

APA Click to copy
Agwa, S. O., Yahya, E., & Ismail, Y. (2013). Design techniques for variability mitigation.

Chicago/Turabian Click to copy
Agwa, Shady O., Eslam Yahya, and Y. Ismail. “Design Techniques for Variability Mitigation” (2013).

MLA Click to copy
Agwa, Shady O., et al. Design Techniques for Variability Mitigation. 2013.

BibTeX Click to copy

@article{shady2013a,
  title = {Design techniques for variability mitigation},
  year = {2013},
  author = {Agwa, Shady O. and Yahya, Eslam and Ismail, Y.}
}

Abstract

As the fabrication technology migrated towards the nanometre scale, 22 nm and beyond, yield enhancement has become one of the challenges facing the integrated circuits design community. Delay and power consumption of the manufactured chips deviate from their predesigned values due to process, voltage and temperature (PVT) variations. This deviation can lead to a considerable loss in yield and reliability. In this paper, we classify and survey the approaches developed to mitigate the PVT variations on the circuit and architectural levels.