Shady Agwa - Layout-Based Evaluation of Read/Write Performance of

Journal article

O. Afuye, Shady Agwa, C. Batten, A. Apsel
European Solid-State Device Research Conference, 2021

Cite

APA Click to copy
Afuye, O., Agwa, S., Batten, C., & Apsel, A. (2021). Layout-Based Evaluation of Read/Write Performance of SOT-MRAM and SOTFET-RAM. European Solid-State Device Research Conference.

Chicago/Turabian Click to copy
Afuye, O., Shady Agwa, C. Batten, and A. Apsel. “Layout-Based Evaluation of Read/Write Performance of SOT-MRAM and SOTFET-RAM.” European Solid-State Device Research Conference (2021).

MLA Click to copy
Afuye, O., et al. “Layout-Based Evaluation of Read/Write Performance of SOT-MRAM and SOTFET-RAM.” European Solid-State Device Research Conference, 2021.

BibTeX Click to copy

@article{o2021a,
  title = {Layout-Based Evaluation of Read/Write Performance of SOT-MRAM and SOTFET-RAM},
  year = {2021},
  journal = {European Solid-State Device Research Conference},
  author = {Afuye, O. and Agwa, Shady and Batten, C. and Apsel, A.}
}

Abstract

This paper presents a comparison of array-level performance of non-volatile SOT-MRAM and SOTFET-RAM to conventional 6T CMOS SRAM using a specially developed simulation suite that merges physics-based compact models and layout-based parasitic extraction. Unlike prior work, our characterization framework generates a full layout of the memory array including all peripheral logic and routing. The framework uses an industry-standard parasitic extraction tool to generate the full netlist including parasitics which is then simulated using compact models for the appropriate emerging non-volatile device. Using this framework, we show about 1.8x energy savings for total read operations and write operations, and 2x area savings for the SOT-based memories relative to a comparable CMOS SRAM for a $256\times 128$ array size. Our unique full-layout approach also enables important insights that challenge conventional wisdom based on higher-level modeling.