Shady Agwa

Research Fellow

RRAM-Based Analogue Artificial Neuron for Gaussian Activation Function Edge Classifier


Journal article


G. Papandroulidakis, Shady O. Agwa, T. Prodromakis
International Symposium on Circuits and Systems, 2025

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APA   Click to copy
Papandroulidakis, G., Agwa, S. O., & Prodromakis, T. (2025). RRAM-Based Analogue Artificial Neuron for Gaussian Activation Function Edge Classifier. International Symposium on Circuits and Systems.


Chicago/Turabian   Click to copy
Papandroulidakis, G., Shady O. Agwa, and T. Prodromakis. “RRAM-Based Analogue Artificial Neuron for Gaussian Activation Function Edge Classifier.” International Symposium on Circuits and Systems (2025).


MLA   Click to copy
Papandroulidakis, G., et al. “RRAM-Based Analogue Artificial Neuron for Gaussian Activation Function Edge Classifier.” International Symposium on Circuits and Systems, 2025.


BibTeX   Click to copy

@article{g2025a,
  title = {RRAM-Based Analogue Artificial Neuron for Gaussian Activation Function Edge Classifier},
  year = {2025},
  journal = {International Symposium on Circuits and Systems},
  author = {Papandroulidakis, G. and Agwa, Shady O. and Prodromakis, T.}
}

Abstract

The computational bottlenecks encountered for memory access and data transfer in modern computing systems, especially for edge computing, require innovations both at device level and architectural level. Emerging technologies, like Resistive RAM (RRAM), can be used to develop novel analogue circuits and systems used to perform cornerstone machine learning operations in the analogue domain, without requiring data conversion in edge applications. In this work, we present RRAM-based artificial neurons used to implement Gaussian Activation Functions (GAFs) aimed at energy efficient analogue Radial Basis Function NNs (RBFNNs) implementation. We are show-casing a configurable RRAM-CMOS circuit emulating GAF-based neuron designed using a commercially available 180nm CMOS technology and in-house RRAM model, operated at 3.3V and 100MHz while dissipating 140fJ per cell per operation. We aim at using this cell as building block for designing a proof-of-concept memory-centric edge classifier. Through the capability of processing analogue information, the circuit can be used to process analogue information in near-sensor computing paradigms.